瑞薩RZ/N2L MPU

RZ/N2L是一種工業(yè)以太網(wǎng)通信用MPU，可輕松將網(wǎng)絡(luò)功能添加到工業(yè)設(shè)備中。它搭載支持TSN的三端口千兆以太網(wǎng)交換機(jī)和EtherCAT從控制器，可支持EtherCAT、PROFINET RT/IRT、EtherNet/IP、OPC UA等主要的工業(yè)以太網(wǎng)通信協(xié)議。它對(duì)網(wǎng)絡(luò)專用配套芯片加以優(yōu)化，無(wú)需大幅改變?cè)O(shè)備的內(nèi)部配置即可直接連接并快速訪問(wèn)外部應(yīng)用主機(jī)CPU。此外，Arm Cortex-R52的最大工作頻率為400MHz，外設(shè)功能包括帶ECC的大容量RAM與ΔΣ I/F、A/D轉(zhuǎn)換器、PWM定時(shí)器、UART和CAN等，可在單個(gè)芯片上實(shí)現(xiàn)遠(yuǎn)程I/O、傳感器集線器、變頻器和網(wǎng)關(guān)。

RZ/N2L PN例程，SDRAM接口片選使用的是CS2（因?yàn)镽ZN2L RSK 的特殊硬件設(shè)計(jì)），而根據(jù)UM，系統(tǒng)里使用單片SDRAM的話，BSC必須CS3#。本文將為您演示為了適配使用CS3的硬件要求，PN的代碼需要做的三處修改。

1

修改 hal_entry.c 文件中 bsp_sdram_init() 函數(shù)，把與CS2相關(guān)的配置屏蔽掉，如下面代碼所示。

#if 0 ~ #endif 之間代碼，60~86行：

static void bsp_sdram_init (void)
{


    volatile uint32_t val;


    R_RWP_S->PRCRS  = 0x0000A50F;
    R_RWP_NS->PRCRN = 0x0000A50F;


    /* NOTE: Port setting and CKIO configuration should have been done before */


    // Configure clock frequency
    val = R_SYSC_NS->SCKCR;
    val &= ~(7<<16);
    //val |=  (6<<16);// CKIO clock: 25MHz 
    val |=  (1<<16);// CKIO clock: 66.7MHz
    R_SYSC_NS->SCKCR = val;


    /* Enable BSC and CKIO module */
    val = R_SYSC_NS->MSTPCRA;
    val &= ~(1<<0);
    R_SYSC_NS->MSTPCRA = val;
    val = R_SYSC_NS->MSTPCRA;        // dummy read: step1


    // Enable CKIO module
    val = R_SYSC_NS->MSTPCRD;
    val &= ~(1<<11);
    R_SYSC_NS->MSTPCRD = val;
    val = R_SYSC_NS->MSTPCRD;        // dummy read: step1
    
    R_RWP_NS->PRCRN = 0x0000A500;
    R_RWP_S->PRCRS  = 0x0000A500;


    /* Wait */
val = R_BSC->CSnBCR[3];        // dummy read: step2
val = R_BSC->CSnBCR[3];        // dummy read: step2
val = R_BSC->CSnBCR[3];        // dummy read: step2
val = R_BSC->CSnBCR[3];        // dummy read: step2
val = R_BSC->CSnBCR[3];        // dummy read: step2


    /* SDRAM:W9825G6KH-6 */
    /* Row address: A0-A12. Column address: A0-A8. */
val = ( 2 <<  9)// BSZ: data bus witdh: 16-bits
 | ( 1 << 11)// Reserved
 | ( 4 << 12)// TYPE: SDRAM
 | ( 0 << 16)// IWRRS: Idle State Insertion between Read-Read Cycles in the Same CS Space
 | ( 0 << 19)// IWRRD: Idle State Insertion between Read-Read Cycles in Different CS Spaces
 | ( 0 << 22)// IWRWS: Idle State Insertion between Read-Write Cycles in the Same CS Space
 | ( 0 << 25)// IWRWD: Idle State Insertion between Read-Write Cycles in Different CS Spaces
 | ( 0 << 28);// IWW: Idle Cycles between Write-Read Cycles and Write-Write Cycles
    R_BSC->CSnBCR[3] = val;


    /* Wait cycle */
val = ( 2 <<  0)// WTRC: Number of Idle states frmo REF Command/Self-refresh relase to ACTV/REF/MRS command
 | ( 2 <<  3)// TRWL: Number of Auto-precharge startup Wait Cycle
 | ( 1 <<  7)// A3CL: CAS Latency: 2
 | ( 1 << 10)// WTRCD: Number of Waits between ACTV command and READ/WRIT command
 | ( 1 << 13);// WTRP: Number of Auto-precharge completion wait states        
        R_BSC->CS3WCR_1 = val;


#if 0
    /* Wait */
val = R_BSC->CSnBCR[2];        // dummy read: step2
val = R_BSC->CSnBCR[2];        // dummy read: step2
val = R_BSC->CSnBCR[2];        // dummy read: step2
val = R_BSC->CSnBCR[2];        // dummy read: step2
val = R_BSC->CSnBCR[2];        // dummy read: step2




    /* SDRAM:W9825G6KH-6 */
    /* Row address: A0-A12. Column address: A0-A8. */
val = ( 2 <<  9)// BSZ: data bus witdh: 16-bits
 | ( 1 << 11)// Reserved
 | ( 4 << 12)// TYPE: SDRAM
 | ( 0 << 16)// IWRRS: Idle State Insertion between Read-Read Cycles in the Same CS Space
 | ( 0 << 19)// IWRRD: Idle State Insertion between Read-Read Cycles in Different CS Spaces
 | ( 0 << 22)// IWRWS: Idle State Insertion between Read-Write Cycles in the Same CS Space
 | ( 0 << 25)// IWRWD: Idle State Insertion between Read-Write Cycles in Different CS Spaces
 | ( 0 << 28);// IWW: Idle Cycles between Write-Read Cycles and Write-Write Cycles
    R_BSC->CSnBCR[2] = val;


   /* Wait cycle */
    val = ( 1 <<  7)// A3CL: CAS Latency: 2
 | ( 1 << 10);// Reserved 1
 
    R_BSC->CS2WCR_1 = val;
#endif
    /* SDRAM control */
    R_BSC->SDCR = 0x00110811;// auto-refresh, auto-precharge mode, Col 9-bits, Row 13-bits


    /* Refresh setting for SDRAM */
    R_BSC->RTCOR = BSC_PROTECT_KEY 
                 | ( 29 <<  0);        // Refresh Time: 29 counts
    R_BSC->RTCSR = BSC_PROTECT_KEY 
                 | (  0 <<  7)         // Compare match Flag: clear
                 | (  0 <<  6)         // Compare match interrupt enable: Disabled
                 | (  2 <<  3)         // Refresh timer count clock: CKIO/16
                 | (  0 <<  0);        // Refresh count: 1 time
                 
    /* wait 200us*/
    R_BSP_SoftwareDelay(200, BSP_DELAY_UNITS_MICROSECONDS);


    /* Power-on Sequence */
    /* Set mode register of SDRAM. needs wait for 2 SDRAM clock after set. */
    *((uint16_t *)0x80212040) = 0x0000;   // Burst length=1, Sequential, CL=2, Burst read and burst write
    *((uint16_t *)0x80211040) = 0x0000;   // Burst length=1, Sequential, CL=2, Burst read and burst write


}

2

pnip_reg.h 頭文件，將CS2 Region的地址定義修改為CS3的Memory Region，如下圖將0x54xxxxxx地址修改為0x58xxxxxx地址。

#ifdef _RENESAS_RZN_
#define U_PNIP__BASE    (0x58000000 + PNIP_DEV_TOP_BASE)
#define U_PNIP__END    (0x581FFFFF + PNIP_DEV_TOP_BASE)
#define U_PERIF_AHB__BASE (0x58200000 + PNIP_DEV_TOP_BASE)
#define U_PERIF_AHB__END  (0x583FFFFF + PNIP_DEV_TOP_BASE)
#endif

3

修改Linker文件中SDRAM Adddress相關(guān)Region定義。

以IAR的 fsp_xspi0_boot.icf 為例：

文件中定義了

1

RAM_Region

地址空間為：0x7440 0010 – 0x744F FFFF;

需要修改為：0x7840 0010 - 0x784F FFFF;

2

Heap_Region

地址空間為：0x5500 0000 – 0x555F FFFF;

需要修改為：0x5900 0000 – 0x595F FFFF;

3

SDRAM_NC_region

地址空間為：0x5450 0000 – 0x547F FFFF;

需要修改為：0x5850 0000 – 0x587F FFFF;